Tegra210: clear PMC_DPD registers on resume

This patch clears the PMC's DPD registers on resuming from System
Suspend, for all Tegra210 platforms that support the sc7entry-fw.

Change-Id: I7881ef0a5f609ed28b158bc2f4016abea3c7f305
Signed-off-by: kalyani chidambaram <[email protected]>

diff --git a/plat/nvidia/tegra/common/drivers/pmc/pmc.c b/plat/nvidia/tegra/common/drivers/pmc/pmc.c
index 30ebdc59df15c34ba6ef2c7ec3d00d0b6bc87a4c..6c5a73bafd86a35df1b8cd31e4ae6b3fbb8a07bf 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/pmc/pmc.c
+++ b/plat/nvidia/tegra/common/drivers/pmc/pmc.c
@@ -122,6 +122,20 @@ bool tegra_pmc_is_last_on_cpu(void)
        return status;
 }
 
+/*******************************************************************************
+ * Handler to be called on exiting System suspend. Right now only DPD registers
+ * are cleared.
+ ******************************************************************************/
+void tegra_pmc_resume(void)
+{
+
+       /* Clear DPD sample */
+       mmio_write_32((TEGRA_PMC_BASE + PMC_IO_DPD_SAMPLE), 0x0);
+
+       /* Clear DPD Enable */
+       mmio_write_32((TEGRA_PMC_BASE + PMC_DPD_ENABLE_0), 0x0);
+}
+
 /*******************************************************************************
  * Restart the system
  ******************************************************************************/

diff --git a/plat/nvidia/tegra/include/drivers/pmc.h b/plat/nvidia/tegra/include/drivers/pmc.h
index c376440f38784a3f5612a54d8e389be0f3459154..32252a28b40ae174c197c584129e71b66c8e0686 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/pmc.h
+++ b/plat/nvidia/tegra/include/drivers/pmc.h
@@ -14,6 +14,7 @@
 #include <tegra_def.h>
 
 #define PMC_CONFIG                             U(0x0)
+#define PMC_IO_DPD_SAMPLE                      U(0x20)
 #define PMC_DPD_ENABLE_0                       U(0x24)
 #define PMC_PWRGATE_STATUS                     U(0x38)
 #define PMC_PWRGATE_TOGGLE                     U(0x30)
@@ -22,6 +23,7 @@
 #define PMC_CRYPTO_OP_0                                U(0xf4)
 #define  PMC_TOGGLE_START                      U(0x100)
 #define PMC_SCRATCH39                          U(0x138)
+#define PMC_SCRATCH41                          U(0x140)
 #define PMC_SECURE_SCRATCH6                    U(0x224)
 #define PMC_SECURE_SCRATCH7                    U(0x228)
 #define PMC_SECURE_DISABLE2                    U(0x2c4)
@@ -53,6 +55,7 @@ void tegra_pmc_cpu_on(int32_t cpu);
 void tegra_pmc_cpu_setup(uint64_t reset_addr);
 bool tegra_pmc_is_last_on_cpu(void);
 void tegra_pmc_lock_cpu_vectors(void);
+void tegra_pmc_resume(void);
 __dead2 void tegra_pmc_system_reset(void);
 
 #endif /* PMC_H */

diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index fde804d040ecce84a4c9f2cd5859c5fb6ce3ae6c..7907e4606269b9daa90c0784869d5f7c24bd3b11 100644 (file)
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -495,6 +495,12 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
         */
        tegra_fc_lock_active_cluster();
 
+       /*
+         * Resume PMC hardware block for Tegra210 platforms supporting sc7entry-fw
+         */
+       if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U))
+               tegra_pmc_resume();
+
        return PSCI_E_SUCCESS;
 }